semiconductor technical data 1 rev 2 ? motorola, inc. 1998 1/98
the mpc980 is a 3.3v dual pll clock generator targeted for high end pentium ? and powerpc ? 603/604 personal computers. the mpc980 synthesizes processor as well as pci clocks from a 14.31818mhz external crystal. in addition the device provides two buffered outputs of the 14.31818mhz crystal as well as a 40mhz scsi clock, a 24mhz floppy clock and a 12mhz keyboard clock. one of the buffered 14.31818mhz outputs can be configured to provide a 16mhz output rather than the second copy of the 14.31818mhz output. ? provides processor and system clocks for pentium ? designs ? provides processor and system clocks for powerpc ? 603/604 designs ? two fully integrated phaselocked loops ? cycletocycle jitter of 150ps ? operates from 3.3v supply ? 52lead lqfp packaging the processor clock outputs of the mpc980 can be programmed to provide 50, 60 or 66mhz. under all processor output frequencies the pci clock outputs will be equal to one half the processor clock outputs. the pci outputs will run synchronously to the processor clock outputs. there are a total of ten output clocks which can be split into a group of four and a group of six. either group can be configured as processor or pci clocks. each of the outputs can drive two series terminated transmission lines allowing for the driving of up to twelve independent processor loads and eight pci clock loads. a pin selectable option is available to delay the pci clock outputs relative to the processor clocks. the amount of delay is a function of the processor clock frequency and varies from 2ns to 6ns. the output jitter of the the pll at 66mhz output is 150ps peaktopeak, cycletocycle (the worst case deviation of the clock period is guaranteed to be less than 150ps). the skews between one processor clock and any other processor clock (or one pci clock to any other pci clock) is 350ps. the worst case skew between the processor clocks and the pci clocks is 500ps. an output enable pin is provided to tristate all of the outputs for board level test. in addition a testing mode is provided to allow for the bypass of the pll's for board level functional debug. pentium is a trademark of intel corporation. powerpc is a trademark of international business machines corporation. dual 3.3v pll clock generator fa suffix 52lead lqfp package case 848d03
mpc980 motorola eclinps and eclinps lite dl140 e rev 3 2 figure 1. logic diagram processor clock pll test mode xtal osc 14.31818mhz fsel0:1 dly_pci 2 2/ 4 4 2 qp0:3 4 qp4:5_qpci4:5 2 qpci0:3 4 q14.3m q14_16m 16mhz 12mhz 16m_sel q12m q24m q40m 24mhz 40mhz system clock pll tclk oe 0 1 0 1 tclk_sel fsel2 table 1. pin descriptions pin label w description 1 vcca analog vcc for system pll use filter (note 1.) 2 tclk_sel 50k sel ext'l tclk or internal xtal ref 3 tclk none external lvcmos ref signal 4 xtal1 none xtal pin 1 5 xtal2 none xtal pin 2 6 gnd system ground input 7 dly_pci 50k sets qp & qpi relationship (see function table 2 on page 3.) 8 vcci vcc pin for internal circuits 9 fsel0 50k least bit for qp/qpi output funct (see function table 1 on page 3.) 10 fsel1 50k most bit for qp/qpi output function (see function table 1 on page 3.) 11 fsel2 50k selection of qp/qpi output funct (see function table 4 on page 3.) 12 vcca analog vcc proc'ssr pll use filter (note 1.) 13 gnda system ground input 14 16m_sel 50k selects 16mhz / 14mhz for q14_16m output 15 q14_16m output for 16mhz / 14mhz xtal osc 16 gnd0 system ground input 17 vcc0 vcc in for the cmos outputs 18 q14m cmos output for 14.3mhz xtal osc 19 gnd0 system ground input 20 qp0 cmos output qp0 21 vcc0 vcc in for the cmos outputs 22 qp1 cmos output qp1 23 gnd0 system ground input 24 qp2 cmos output qp2 25 vcc0 vcc in for the cmos outputs pin label w description 26 gndi system ground input 27 vcco vcc in for the cmos outputs 28 qp3 cmos output qp3 29 gnd0 system ground input 30 gnd0 system ground input 31 qp4_pci4 cmos output qp4_pci4 32 vcc0 vcc in for the cmos outputs 33 qp5_pci5 cmos output qp5_pci5 34 gnd0 system ground input 35 gnd0 system ground input 36 qpci3 cmos output qpci3 37 vcco vcc in for the cmos outputs 38 qpci2 cmos output qpci2 39 gnd0 system ground input 40 vcci vcc for internal core logic 41 gnd0 system ground input 42 qpci1 cmos output qpci1 43 vcc0 vcc in for the cmos outputs 44 qpci0 cmos output qpci0 45 gnd0 system ground input 46 qm12 cmos output qm12 47 vcc0 vcc in for the cmos outputs 48 q40m cmos output q40m 49 gnd0 system ground input 50 q24m cmos output q24m 51 oe 50k select output state (see function table 1 on page 3.) 52 gnd0 system ground input 1. the filter recommended for the analog power pins is found in figure 3 in the applications information section on page 5.
mpc980 eclinps and eclinps lite dl140 e rev 3 3 motorola figure 2. 52lead pinout (top view) vcci gnd0 qpci1 vcc0 qpci0 gnd0 q12m vcc0 q40m gnd0 q24m oe gnda gndi vcc0 qp2 gnd0 qp1 vcc0 qp0 gnd0 q14m vcc0 gnd0 q14_16m 16m_sel gnd0 qpci2 vcc0 qpci3 gnd0 gnd0 qp5_pci5 vcc0 qp4_pci4 gnd0 gnd0 qp3 vcc0 tclk_sel vcca tclk xtal1 xtal2 gnd dly_pci vcci fsel0 fsel1 fsel2 vcca gnda 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 12345678910111213 39 38 37 36 35 34 33 32 31 30 29 28 27 26 mpc980 function table 1 oe fsel0 fsel1 qp qpci q14m q16m q24m q12m q40m 0 x x high impedance high impedance hi z hi z hi z hi z hi z 1 0 0 50mhz 25mhz 14.31818 16 24 12 40 1 0 1 60mhz 30mhz 14.31818 16 24 12 40 1 1 0 66mhz 33mhz 14.31818 16 24 12 40 1 1 1 tclk/2 tclk/4 tclk tclk/6 tclk/4 tclk/8 tclk/2 function table 2 dly_pci qp/qpci relationship 0 1 synchronous processor & pci clocks pci clocks lag processor clocks function table 3 tclk_sel pll input reference 0 1 crystal oscillator tclk function table 4 fsel2 qp/qpci output configuration 0 1 6 processor and 4 pci clocks 4 processor and 6 pci clocks function table 5 16m_sel q14_16m output configuration 0 1 14.31818mhz to q14_16m out 16mhz to q14_16m out
mpc980 motorola eclinps and eclinps lite dl140 e rev 3 4 dc characteristics (t a = 0 to 70 c) symbol characteristic min typ max unit condition v cc power supply voltage 3.35% 3.3 3.3+5% v v il input low voltage 0.3v cc v v ih input high voltage 0.7v cc v cc v v oh output high voltage v cc 0.4 v 20ma (note 1.) v ol output low voltage 0.4 v +20ma (note 1.) c in input capacitance 4.5 pf c pd power dissipation capacitance 25 pf i cc quiescent supply current 190 ma i cca pll supply current 20 ma 1. output can drive two series terminated 50 w transmission lines or a single 50 w line terminated 50 w into v cc /2. ac characteristics (t a = 0 to 70 c, v cc = 3.3v 5%) symbol characteristic min typ max unit condition f xtal input crystal frequency 14.31818 mhz f max maximum output frequency qp qpci 66 33 mhz t dc output duty cycle t cycle /2 1000 t cycle /2 500 t cycle /2 +1000 ps t jitter cycletocycle jitter 66/33mhz (peaktopeak) 60/30mhz 50/25mhz 150 200 250 ps t skew outputtooutput skew qp to qp qpci to qpci qp to qpci 350 350 500 ps rising edges only; dly_pci = 0 t delay time delay qp to qpci 2 1 4f qp 1 4f qp 1 ns dly_pci = 1 t r , t f output rise/fall time 0.05 0.8 ns 1.0 to 1.8v t lock pll lock time 10 ms t pzl , t pzh output enable time 3 10 ns 50 w to v cc /2 t plz , t phz output disable time 4 11 ns 50 w to v cc /2 applications information using the onboard crystal oscillator the mpc980 features an onboard crystal oscillator to allow for seed clock generation as well as final distribution. the onboard oscillator is completely self contained so that the only external component required is the crystal. as the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the mpc980 as possible to avoid any board level parasitics. to facilitate colocation surface mount crystals are recommended, but not required. the oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large onboard capacitors. because the design is a series resonant design for the optimum frequency accuracy a series resonant crystal should be used (see specification table below). unfortunately most off the shelf crystals are characterized in a parallel resonant mode. however a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel
mpc980 eclinps and eclinps lite dl140 e rev 3 5 motorola resonant mode. therefore in the majority of cases a parallel specified crystal can be used with the mpc980 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. typically a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. for most processor implementa tions a few hundred ppm translates into khz inaccuracies, a level which does not represent a major issue. table 2. crystal specifications parameter value crystal cut fundamental at cut resonance series resonance* frequency tolerance 75ppm at 25 c frequency/temperature stability 150ppm 0 to 70 c operating range 0 to 70 c shunt capacitance 57pf equivalent series resistance (esr) 50 to 80 w max correlation drive level 100 m w aging 5ppm/yr (first 3 years) * see accompanying text for series versus parallel resonant discussion. power supply filtering the mpc980 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the mpc980 provides separate power supplies for the output buffers (vcco) and the phaselocked loop (vcca) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phaselocked loop. in a controlled environment such as an evaluation board this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is a power supply filter on the vcca pin for the mpc980. figure 3 illustrates a typical power supply filter scheme. the mpc980 is most susceptible to noise with spectral content in the 1khz to 1mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the vcca pin of the mpc980. from the data sheet the i vcca current (the current sourced per vcca pin) is typically 15ma (20ma maximum), assuming that a minimum of 3.0v must be maintained on the vcca pin very little dc voltage drop can be tolerated when a 3.3v v cc supply is used. the resistor shown in figure 3 must have a resistance of 1015 w to meet the voltage drop criteria. the rc filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20khz. as the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. it is recommended that the user start with an 810 w resistor to avoid potential v cc drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed. figure 3. power supply filter pll_vcc vcc mpc980 vcca pins 1 & 12 0.01 m f 22 m f 0.01 m f 3.3v r s =515 w although the mpc980 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. component reliability analysis information all inputs and outputs of the mpc980 clock generator are lvcmos and are not 5v tolerant. the quiescent current is 190ma maximum, so the maximum quiescent power is (190ma) (3.465v maxv cc ) = 658.35mw. total maximum power must include the dynamic power of the outputs. dynamic power/output = [logic swing out (volts)] [v cc (volts)] [freq (mhz)] [c l + c p (pf)] where c l = load capacitance c p = output power dissipation capacitance the mpc980 is packaged in a 52lead lqfp to optimize board space and power supply distribution. the lqfp package occupies a 12mm x 12mm space on the pcb. the 52pin lqfp package has a q ja of 64 to 74 c/w in still air and a q ja of 42 to 52 c/w in 500lfpm of moving air. the maximum chip temperature for the device is 140 c. the device component count is: npn bipolar devices 2,238; nmos devices 1,313; pmos devices 281.
mpc980 motorola eclinps and eclinps lite dl140 e rev 3 6 outline dimensions fa suffix plastic lqfp package case 848d-03 issue d f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums l, m and n to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane t. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). ???? ???? view aa ab ab view y section abab rotated 90 clockwise dim a min max min max inches 10.00 bsc 0.394 bsc millimeters a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c 1.70 0.067 c1 0.05 0.20 0.002 0.008 c2 1.30 1.50 0.051 0.059 d 0.20 0.40 0.008 0.016 e 0.45 0.030 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.75 0.018 0.026 bsc j 0.07 0.20 0.003 0.008 k 0.50 ref 0.020 ref r1 0.08 0.20 0.003 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref c l x x=l, m, n 1 13 14 26 27 39 40 52 4x 13 tips 4x n 0.20 (0.008) h lm n 0.20 (0.008) t lm seating plane c 0.10 (0.004) t 4x 3 4x 2 s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z s lm m 0.13 (0.005) n s t plating base metal d j u b v b1 a s v1 a1 s1 l n m h t 1 g q 1 q q 3 q 2 07 12 07 0 0 ref 12 ref 3x view y view aa 2x r r1 12 ref 12 ref
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